How silicon spin qubits work
How the spin of one electron in a silicon quantum dot becomes a qubit, how the chips are made in CMOS fabs, how gates and readout work, and why variability and wiring limit scale.
A spin qubit stores information in the spin of a single electron, or a hole, trapped in a quantum dot tens of nanometers across and defined by gate electrodes on a silicon chip. The device is essentially a transistor, so the field can draw on the fabs, wafers and tools of the chip industry, and a qubit takes about 1,000 to 10,000 times less area than a superconducting one. Today's trade-offs are small systems, of up to 18 qubits, and qubits that each behave a little differently. Intel, Diraq, HRL Laboratories, Quantum Motion, imec, QuTech and Silicon Quantum Computing are among the leaders.
This article is part of a series on the main ways to build a qubit. The overview compares all six side by side.
How the qubit forms
In a magnetic field, an electron's spin-up and spin-down states have different energies. For electrons in silicon the splitting is about 28 GHz per tesla, so typical fields of 0.2 to 1 tesla put the qubit at roughly 5 to 30 GHz, in the microwave band.
Voltages on metal gates about 50 to 100 nanometers wide form tiny potential wells, the quantum dots, each holding one electron. Three material stacks lead. Electrons sit in strained silicon between silicon-germanium layers (Intel, QuTech, HRL), or at a silicon-oxide interface as in a transistor channel (Diraq, Quantum Motion, imec). Holes in germanium have strong spin-orbit coupling, which allows all-electrical control. A related approach places single phosphorus atoms in silicon and uses the bound electron and the nucleus as qubits (Silicon Quantum Computing).
Natural silicon contains 4.7% silicon-29, whose nuclear spins create magnetic noise, and isotopically enriched silicon-28 removes most of it. The best foundry-made device so far, from Diraq and imec on a 300 mm line, kept its phase for 30 microseconds (µs) without echo pulses and 0.8 milliseconds (ms) with a refocusing echo, and held its energy for 6.3 seconds. Typical arrays fall well short of that, as the section on scaling below explains.
Most designs use one spin per dot as the qubit and drive it with microwaves. HRL encodes each qubit in three spins across three dots, so every gate is a voltage pulse and no microwaves are needed.
How the chips are made
Spin-qubit chips use the processes of the semiconductor industry. Intel builds silicon-germanium devices on its 300 mm line in Oregon with extreme-ultraviolet lithography. imec runs a 300 mm silicon-oxide process, and in a 2025 Nature paper randomly chosen devices from it exceeded 99% fidelity for every operation. HRL uses 200 mm isotopically enriched wafers.
Testing works like a fab, too. Intel's cryogenic 300 mm wafer prober measures hundreds of devices at 1.6 kelvin; it found 99.8% of quantum dots and 96% of complete devices working.
The gate stack has two or three overlapping layers. Plunger gates set each dot's energy, barrier gates between dots set the coupling, and sensor dots at the edge of the array detect charge. Silicon devices often add a cobalt micromagnet to drive and address the spins.
How it is controlled and read out
Single-qubit gates use a microwave antenna on the chip, or a microwave voltage on a gate that shakes the electron in the micromagnet's field gradient; in germanium, spin-orbit coupling does the same without a magnet. Fidelities of 99.9% and above are now routine in the best devices: HRL reports 99.98% for its three-spin qubits, and Silicon Quantum Computing up to 99.99% on donor atoms.
Two-qubit gates pulse the barrier gate between neighboring dots, turning on an exchange interaction for about 10 to 200 nanoseconds (ns). Most published devices reach 99 to 99.8%: QuTech and RIKEN passed 99%, at about 99.5%, in 2022, and three Diraq devices spanned 98.4 to 99.78%. HRL's 18-qubit processor averages 99.65%, with its best pair at 99.91% (Nature, July 2026), a single-lab result.
Readout converts spin into charge. In Pauli spin blockade, two electrons can share one dot only in one particular joint spin state. A nearby single-electron transistor senses whether the charge moved, often by radio-frequency reflectometry, in microseconds at 99 to 99.9% fidelity. Readout is slower than the gates and dominates the time of an error-correction cycle.
Control electronics are moving into the refrigerator. HRL's processor is driven by a controller at 4 kelvin with about 70 million transistors, which draws under 3.5 watts and puts less than 10 microwatts of heat on the qubit stage.
What makes it hard to scale
No two dots are alike. Each dot differs slightly in frequency, valley splitting and local noise, and drifts over time, so each needs its own tuning. Across Intel's 12-qubit arrays, coherence without echo was 1.3 ± 0.5 µs, far below the best single devices, and Diraq needed live feedback on up to nine settings per device.
Charge noise. Fluctuating defects in oxides and interfaces shift the dots' potentials and, with them, the qubit frequencies.
Valley splitting. Silicon's conduction band has nearly equal energy valleys. Where the gap between them is small, qubits leak and relax, and the gap varies across a wafer.
Wiring. Every qubit needs several gate electrodes, and dense 2D arrays struggle to route lines between the dots. Coaxial cable from room temperature does not scale past a few hundred qubits.
Connectivity. The exchange interaction reaches only neighbors about 100 nm apart, so arrays are 1D chains or small 2D grids. The largest 2D control demonstration has about 10 qubits.
Heat budget. A dilution refrigerator offers only about 10 to 20 microwatts of cooling at 10 to 20 millikelvin (mK), which limits the electronics that can sit next to the qubits.
Scale. Published processors have about 6 to 18 qubits.
What could solve it
Real-time feedback. Tracking each qubit's drifting settings on fast FPGA hardware and correcting the next pulses kept Diraq's two-qubit gates above 99% repeatably. Diraq argues that this lets fast, dense spin qubits win at scale; that is its own view.
Cryogenic CMOS. Controllers at 4 kelvin (HRL, Intel) and electronics at millikelvin beside the qubits (Diraq with Emergence Quantum and the University of Sydney, Nature 2025) cut wiring without degrading the qubits.
Warmer qubits. Running at 1 kelvin or above gives hundreds to thousands of times more cooling power. Diraq and UNSW showed 99.85% single-qubit and 98.92% two-qubit gates above 1 kelvin (Nature, 2024).
Shuttling. Moving electrons in traveling potential wells links distant qubits; QuTech ran two-qubit gates on moving spins at about 99% fidelity (Nature, May 2026).
Shared control lines. Crossbar arrays share gates across rows and columns, which cuts the number of lines from about N to about the square root of N.
Industrial fabs and purer materials. 300 mm lines at Intel, imec, GlobalFoundries and CEA-Leti, and further isotope purification. In July 2026 IBM agreed to acquire HRL and plans to run its spin qubits alongside its superconducting work.
Strengths and limits
Strengths. Tiny qubits, with dots about 50 to 100 nm apart, so millions per chip are physically plausible; manufacturing in existing CMOS fabs; fast gates of 10 to 200 ns; single-qubit fidelity of 99.9% and above; operation shown above 1 kelvin; and voltage-only control in some designs.
Limits. Small systems of 18 qubits or fewer; per-dot variability and complex tuning; charge noise and valley splitting; nearest-neighbor connectivity until shuttling matures; severe wiring for dense arrays; and readout slower than the gates.
Key numbers
Two-qubit gates: typically 99 to 99.8%; HRL's average 99.65% and best pair 99.91% (single lab, 2026).
Single-qubit gates: 99.98% (HRL); up to 99.99% (Silicon Quantum Computing, donor atoms).
Gate time: about 10 to 200 ns.
Coherence, best foundry device: 30 µs without echo, 0.8 ms with echo, 6.3 s energy lifetime (Diraq and imec).
Coherence across an array: 1.3 ± 0.5 µs without echo (Intel, 12 qubits).
Largest processor: 18 qubits from 54 dots, with a 4 kelvin controller (HRL, 2026).
Wafer yield: 99.8% of dots and 96% of devices working (Intel, 300 mm wafers).
Operating temperature: typically 10 to 150 mK; above 1 kelvin demonstrated.
Quick answers
Why build qubits in silicon? Spin qubits are made much like transistors, so they can use the industry's fabs, wafers and tools, and each qubit is tiny. That makes chips with millions of qubits physically plausible, if variability and wiring can be solved.
What is a quantum dot? A tiny region of a semiconductor, tens of nanometers across, where gate voltages trap a single electron or hole. The spin of that charge is the qubit.
How do spin qubits compare with superconducting qubits? Both have gates of tens to hundreds of nanoseconds and are made with lithography. Spin qubits are far smaller, use CMOS fabs and can run warmer, but today's processors are much smaller (18 qubits against 105 to 156 for the largest superconducting processors) and each qubit needs individual tuning.
Who builds silicon spin qubits? Intel, Diraq, HRL Laboratories, Quantum Motion, imec, QuTech, Equal1 and Silicon Quantum Computing, among others.
Sources
Intel, probing single electrons across 300 mm spin qubit wafers, Nature (2024)
Intel, 12-spin-qubit arrays from a 300 mm line, Nano Letters (2025)
Diraq and UNSW, high-fidelity spin qubit operation above 1 kelvin, Nature (2024)
QuTech and TNO, two-qubit logic with moving spins (May 2026)
IBM, agreement to acquire HRL Laboratories (July 2026)
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